The present disclosure relates to power amplifier circuits. Doherty amplifiers are known as high-efficiency power amplifier circuits. A Doherty amplifier typically has a configuration in which a carrier amplifier, which operates irrespective of the power level of an input signal, and a peak amplifier, which is turned off when the power level of the input signal is small and is turned on when the power level of the input signal is large, are connected in parallel with each other. When the power level of the input signal is large, the carrier amplifier operates while maintaining saturation at a saturation output power level. As a result, a Doherty amplifier can realize improved efficiency compared with a normal power amplifier circuit.
As a modification of such a Doherty amplifier, for example, Japanese Unexamined Patent Application Publication No. 2016-19228 discloses a Doherty amplifier that is configured without using a λ/4 line, which is used in typical Doherty amplifiers.
Since the Doherty amplifier disclosed in Japanese Unexamined Patent Application Publication No. 2016-19228 is configured without using a λ/4 line, a reduction in circuit scale can be achieved compared with a typical Doherty amplifier. However, in this configuration, a power-supply choke coil and bypass capacitor are provided in order to suppress generation of noise caused by the power supply circuit. Therefore, further improvements are required when applying this configuration to cellular phone devices for which the demands for reduction of circuit scale have been becoming ever stricter in recent years.